View ICS9DBL411_4302512.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATASHEET
Four Output Differential Fanout Buffer for PCI Express Gen 1 & 2 Recommended Application:
PCI-Express fanout buffer
ICS9DBL411 Features/Benefits:
* * Low power differential fanout buffer for PCIExpress and CPU clocks 20-pin MLF or TSSOP packaging
Output Features:
* * 4 - low power differential output pairs Individual OE# control of each output pair
General Description:
The ICS9DBL411 is a 4 output lower power differential buffer. Each output has its own OE# pin. It has a maximum input frequency of 400 MHz.
Key Specifications:
* * Output cycle-cycle jitter < 25ps additive Output to output skew: < 50ps
Power Groups
Pin Number (TSSOP) VDD GND 9,18 10,17 4 5 Pin Number (MLF) VDD GND 6,15 7,14 1 2 Description DIF(3:0) Analog VDD & GND Description DIF(3:0) Analog VDD & GND
Funtional Block Diagram
4 OE#(3:0)
4 DIF_INT DIF_INC STOP LOGIC DIF_LPR(3:0)
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
1250A--07/31/07
1
ICS9DBL411 Four Output Differential Buffer for PCI Express
Advance Information Pin Configuration
OE0# DIF_INC DIF_INT VDDA GNDA OE3# DIF3C_LPR DIF3T_LPR VDD_IO GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
DIF0T_LPR DIF0C_LPR VDD_IO GND OE1# DIF1T_LPR DIF1C_LPR OE2# DIF2T_LPR DIF2C_LPR
20-pin TSSOP
ICS9DBL411
DIF0T_LPR DIF_INC OE0#
20 19 18 17 16 VDDA GNDA OE3# DIF3C_LPR DIF3T_LPR 1 2 3 4 5 15 14 13 12 11 VDD_IO GND OE1# DIF1T_LPR DIF1C_LPR
9DBL411
6 VDD_IO 7 GND 8 DIF2C_LPR 9 10 DIF2T_LPR OE2#
20-pin MLF
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
DIF0C_LPR
DIF_INT
1250A--07/31/07
2
ICS9DBL411 Four Output Differential Buffer for PCI Express
Advance Information TSSOP Pin Description
PIN # (TSSOP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIN NAME OE0# DIF_INC DIF_INT VDDA GNDA OE3# DIF3C_LPR DIF3T_LPR VDD_IO GND DIF2C_LPR DIF2T_LPR OE2# DIF1C_LPR DIF1T_LPR OE1# GND VDD_IO DIF0C_LPR DIF0T_LPR PIN TYPE IN IN IN PWR GND IN OUT OUT PWR GND OUT OUT IN OUT OUT IN GND PWR OUT OUT DESCRIPTION Output Enable for DIF0 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement side of differential input clock True side of differential input clock 3.3V Power for the Analog Core Ground for the Analog Core Output Enable for DIF3 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Power supply for low power differential outputs, nominal 1.05V to 3.3V Ground pin Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF2 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF1 output. Control is as follows: 0 = enabled, 1 = Low-Low Ground pin Power supply for low power differential outputs, nominal 1.05V to 3.3V Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
1250A--07/31/07
3
ICS9DBL411 Four Output Differential Buffer for PCI Express
Advance Information MLF Pin Description
PIN # (MLF) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIN NAME VDDA GNDA OE3# DIF3C_LPR DIF3T_LPR VDD_IO GND DIF2C_LPR DIF2T_LPR OE2# DIF1C_LPR DIF1T_LPR OE1# GND VDD_IO DIF0C_LPR DIF0T_LPR OE0# DIF_INC DIF_INT PIN TYPE PWR GND IN OUT OUT PWR GND OUT OUT IN OUT OUT IN GND PWR OUT OUT IN IN IN DESCRIPTION 3.3V Power for the Analog Core Ground for the Analog Core Output Enable for DIF3 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Power supply for low power differential outputs, nominal 1.05V to 3.3V Ground pin Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF2 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF1 output. Control is as follows: 0 = enabled, 1 = Low-Low Ground pin Power supply for low power differential outputs, nominal 1.05V to 3.3V Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF0 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement side of differential input clock True side of differential input clock
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
1250A--07/31/07
4
ICS9DBL411 Four Output Differential Buffer for PCI Express
Advance Information
Absolute Maximum Ratings
PARAMETER Maximum Supply Voltage Maximum Supply Voltage Maximum Input Voltage Minimum Input Voltage Storage Temperature Input ESD protection SYMBOL VDDxxx VDDxxx_IO VIH VIL Ts ESD prot CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply 3.3V LVCMOS Inputs Any Input Human Body Model Vss - 0.5 -65 2000 150 0.99 MIN MAX 4.6 3.8 4.6 UNITS Notes V V V V
1,7 1,7 1,7,8 1,7 1,7 1,7
C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER Ambient Operating Temp Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input Slew Rate - DIF_IN Input Leakage Current Operating Supply Current SYMBOL Tambient VDDxxx VDDxxx_IO VIHSE VILSE VIHDIF VILDIF dv/dt IIN IDD_3.3V IDD_IO+100M IDD_IO_400M Standby Current Input Frequency Pin Inductance Input Capacitance IDD_SB33 IDD_SBIO Fi Lpin CIN COUT T OE#LAT TDROE# TFALL TRISE Logic Inputs Output pin capacitance Number of clocks to enable or disable output from assertion/deassertion of OE# Output enable after OE# de-assertion Fall/rise time of OE# inputs 1.5 CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply Single-ended inputs Single-ended inputs Differential inputs Differential inputs Measured differentially VIN = VDD , VIN = GND 3.3V supply VDD_IO supply @ fOP = 100MHz VDD_IO supply @ fOP = 400MHz 3.3V supply, Input stopped 0.8V IO supply, Input stopped VDD = 3.3 V 33 MIN 0 3.135 0.99 2 VSS - 0.3 600 VSS - 0.3 0.4 -5 MAX 70 3.465 3.465 VDD + 0.3 0.8 1.15 300 8 5 25 15 54 25 0.1 400 7 5 6 1 3 10 5 5 UNITS C V V V V V V V/ns uA mA mA mA mA mA MHz nH pF pF periods ns ns ns Notes 1 1 1 1 1 1 1 2 1 1 1 1 1 1 2 1 1 1 1 1 1 1
OE# latency Tdrive_OE# Tfall_OE# Trise_OE#
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
1250A--07/31/07
5
ICS9DBL411 Four Output Differential Buffer for PCI Express
Advance Information
AC Electrical Characteristics - DIF Low Power Differential Outputs
PARAMETER Rising Edge Slew Rate Falling Edge Slew Rate Slew Rate Variation Maximum Output Voltage Minimum Output Voltage Differential Voltage Swing Crossing Point Voltage Crossing Point Variation Duty Cycle Distortion DIF Jitter - Cycle to Cycle DIF[3:0] Skew Propagation Delay PCIe Gen2 Phase Jitter Addtive PCIe Gen2 Phase Jitter Addtive
1 2 3 4 5
SYMBOL tSLR tFLR tSLVAR VHIGH VLOW VSWING VXABS VXABSVAR DCYCDIS1 DCYCDIS2 DIFJ C2C DIFSKEW tPD tphase_addHI tphase_addLO
CONDITIONS Differential Measurement Differential Measurement Single-ended Measurement Includes overshoot Includes undershoot Differential Measurement Single-ended Measurement Single-ended Measurement Dif Measurement, fIN<=267MHz Dif Measurement, fIN>267MHz Differential Measurement, Additive Differential Measurement Input to output Delay 1.5MHz < fIN < Nyquist (50MHz) 10KHz < fIN < 1.5MHz
MIN 1 1
MAX 2.5 2.5 20 1150
UNITS NOTES V/ns V/ns % mV mV mV 1,2 1,2 1 1 1 1 1,3,4 1,3,5 1,6 1,6 1 1 1 1 1
-300 300 300 550 140 +5 +7 25 50 2.5 3.5 0.8 0.1
mV mV % % ps ps ns ps rms ps rms
Notes on Electrical Characteristics:
Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through Vswing centered around differential zero Vxabs is defined as the voltage where CLK = CLK#
Only applies to the differential rising edge (CLK rising and CLK# falling) Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. 6 Tthis is the figure refers to the maximum distortion of the input wave form.
7 8
Operation under these conditions is neither implied, nor guaranteed. Maximum input voltage is not to exceed maximum VDD
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
1250A--07/31/07
6
ICS9DBL411 Four Output Differential Buffer for PCI Express
Advance Information
N
c
L
E1 INDEX AREA
E
12
D
A2 A1
A
20-Lead, 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) (25.6 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 6.40 BASIC 0.252 BASIC E1 4.30 4.50 .169 .177 e 0.65 BASIC 0.0256 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0 8 0 8 aaa -0.10 -.004 VARIATIONS
-Ce
b SEA TING PLANE
N 20
D mm. MIN 6.40 MAX 6.60 MIN .252
D (inch) MAX .260
aaa C
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
Ordering Information
ICS 9DBL411yGLFT
Example:
ICS XXXX y G LF T
Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers)
IDTTM/ICSTM Four Output Differential Buffer for PCI Express 1250A--07/31/07
7
ICS9DBL411 Four Output Differential Buffer for PCI Express
Advance Information
S eating Plane Index Area N Anvil S ingulation A1 A3 L
(R ef.)
(ND -1)x e
(R ef.)
ND & N E ven N
1
(Typ.) e 2 If N & N D
are Even (N -1)x e
2 E2
E2 2
(R ef.)
OR
Top View S awn S ingulation
b A
(R f.) e
e D2 2 D2
D
ND & N Odd C
Thermal Base
Chamfer 4x 0.6 x 0.6 max OPTIONAL
0.08
C
THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE
DIMENSIONS SYMBOL A A1 A3 b e
DIMENSIONS MIN. MAX. 0.8 1.0 0 0.05 0.20 Reference 0.18 0.3 0.50 BASIC SYMBOL N ND NE D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. ICS 20L TOLERANCE 20 5 5 4.00 x 4.00 2.00 / 2.25 2.00 / 2.25 0.45 / 0.65
Ordering Information
ICS 9DBL411yKLFT
Example:
ICS XXXX y K LF T
Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type K = MLF Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers)
IDTTM/ICSTM Four Output Differential Buffer for PCI Express 1250A--07/31/07
8
ICS9DBL411 Four Output Differential Buffer for PCI Express
Advance Information
Revision History
Rev. 0.1 0.2 Issue Date Description Page # 08/01/06 Initial Release. 09/22/06 Updated MLF Package Dimensions. 8 1. Updated electrical characteristics - additive jitter, cycle-to-cycle, tpd, skews, slew rates, Idd, etc. 2. Corrected power grouping table for TSSOP pkg 07/31/07 3. Final Release 1,5,6
A
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015 408-284-8200 Fax: 408-284-2775
For Tech Support
408-284-6578 pcclockhelp@idt.com
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505
Europe
IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339
TM
(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA
IDTTM/ICSTM Four Output Differential Buffer for PCI Express
1250A--07/31/07
9

▲Up To Search▲

Price & Availability of ICS9DBL411

	To Download ICS9DBL411 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .